1. Field of the Invention
The present invention generally relates to the area of Dynamic Random-Access Memory (DRAM) technology, more particularly to an operation frequency adjusting system for DRAM and a method thereof.
2. Description of Related Art
DRAM is a dynamic random access memory, which retains data for only a short period of time. In order to extend data retention time, DRAM adopts a memory capacitor and refreshes the retained data at specific time intervals. The periodic data refreshment is operated and controlled by a DRAM controller. The operation consumes a large amount of electric energy. Therefore, DRAM usually requires a large capacity battery.
As a typical system-on-chip (SOC), a multimedia system-on-chip includes a plurality of functional modules, such as processor, hardware accelerator, and so on. The functional modules operate independently and may need to access to various memory devices. Because some of the functional modules in the multimedia system-on-chip usually store their data on an external DRAM during data processing to reduce the system cost. For a more complicated multimedia system-on-chips, depending on their tasks, the bandwidth requirements of the DRAM may be significantly different. For example, during the process of displaying high-definition streaming media files, the multimedia system-on-chip requires the processor and the hardware accelerator to run at full speed. The operation frequency of the DRAM in this case is typically high (e.g., at least 166 MHz). On the other hand, during the process of displaying MP3 media, the required bandwidth for DRAM operation decreases dramatically (e.g., to 50 MHz). Thus, the power consumption of the multimedia system-on-chip depends on the tasks being performed.
The conventional multimedia system-on-chips ignore the operation frequency characteristics and pre-configure the operation frequency of DRAM only at some specific stages, (for example, at the start time of the system). Therefore, it is difficult to achieve an optimal balance between an efficient operation and the power consumption of a DRAM.
Thus, there is an urgent need for a technology to provide a method for adjusting the operation frequency of DRAM such that an optimal balance between the efficiency and power consumption of DRAM can be obtained, and to enable the system-on-chip to operate at a desired speed and simultaneously achieves improvements in the power consumption.